For higher integration and higher capacity of a nonvolatile semiconductor memory device, it is necessary to reduce design rules. In order to reduce the design rules, further micro fabrication of, for example, a wiring pattern is needed. However, an extremely high level of fabrication technique is required for this purpose, so that the reduction of the design rules has been increasingly difficult.
Accordingly, to enhance the integration of a memory cell, there has recently been suggested a three-dimensional nonvolatile semiconductor memory device comprising a fin structure that includes a structure in which a first oxide layer, a semiconductor layer, and a second oxide layer are stacked in this order.
A memory cell of this nonvolatile semiconductor memory device comprises a gate structure in which a gate oxide layer (tunnel oxide layer), a charge storage layer, a block insulating layer, and a control gate electrode are stacked in this order, for example, on the side surface of the semiconductor layer in the fin structure.
However, in this nonvolatile semiconductor memory device, characteristic improvement of the memory cell is difficult due to specific problems resulting from its manufacturing method.
For example, in the manufacturing method of this nonvolatile semiconductor memory device, a process for recessing the side surface of the semiconductor layer, that is, a process for shrinking the width of the semiconductor layer is employed after the formation of the fin structure. In this case, the side surface of the semiconductor layer is etched into a concave curve. This becomes noticeable when the semiconductor layer is recessed by wet etching (etching that uses a chemical).
This concave curve forms, in the edge of the semiconductor layer on the side of the first and second oxide layers, a tapered portion extending on the side of the charge storage layer. Thus, in the gate oxide layer formed along the concave curve of the semiconductor layer, an electric field concentrates between the tapered portion of the semiconductor layer and the charge storage layer. This leads to characteristic deterioration of the memory cell.
Therefore, when the generation of this concave curve is premised, it is necessary to suggest a new structure and a manufacturing method of the same which lessen the curvature of the concave curve and which prevent a local concentration of the electric field in the gate oxide layer of the memory cell, in order to put the above-mentioned three-dimensional nonvolatile semiconductor memory device into practical use.